In recent years, semiconductor devices have become more integrated, and structures of semiconductor elements have become more complicated. Further, the number of layers in multilayer interconnects used for a logical system has increased. Accordingly, irregularities on a surface of a semiconductor device are increased, so that step heights on the surface of the semiconductor device tend to be large. This is because, in a manufacturing process of a semiconductor device, a thin film is formed on a semiconductor device, then micromachining processes, such as patterning or forming holes, are performed on the semiconductor device, and these processes are repeated to form subsequent thin films on the semiconductor device.
When the number of irregularities is increased on a surface of a semiconductor device, the following problems arise. When a thin film is formed on a semiconductor device, the thickness of the film formed at portions having a step is relatively small. Further, an open circuit may be caused by disconnection of interconnects, or a short circuit may be caused by insufficient insulation between interconnect layers. As a result, good products cannot be obtained, and the yield tends to be lowered. Further, even if a semiconductor device initially works normally, reliability of the semiconductor device is lowered after long-term use. At the time of exposure in a lithography process, if the irradiation surface has irregularities, then a lens unit in an exposure system is locally unfocused. Therefore, if the irregularities of the surface of the semiconductor device are increased, then it becomes problematically difficult to form a fine pattern itself on the semiconductor device.
Thus, in a manufacturing process of a semiconductor device, it becomes increasingly important to planarize a surface of the semiconductor device. The most important one of the planarizing technologies is chemical mechanical polishing (CMP). In the chemical mechanical polishing, with use of a polishing apparatus, while a polishing liquid containing abrasive particles such as silica (SiO2) therein is supplied onto a polishing surface such as a polishing pad, a substrate such as a semiconductor wafer is brought into sliding contact with the polishing surface, so that the substrate is polished.
This type of polishing apparatus includes a polishing table having a polishing surface formed by a polishing pad, and a substrate holding device, which is referred to as a top ring or a carrier head, for holding a substrate such as a semiconductor wafer. When a semiconductor wafer is polished with such a polishing apparatus, the semiconductor wafer is held and pressed against the polishing table under a predetermined pressure by the substrate holding device. At that time, the polishing table and the substrate holding device are moved relative to each other to bring the semiconductor wafer into sliding contact with the polishing surface, so that the surface of the semiconductor wafer is polished to a flat mirror finish.
In the polishing apparatus, assuming that a polishing rate is constant, the amount of polishing is in proportion to a polishing time (processing time) during which a polishing process is performed. Accordingly, the following method is employed to determine a polishing time. First, the film thickness of one substrate is measured before a polishing process. Then, the substrate is polished for a predetermined period of time by a polishing apparatus. The film thickness of the semiconductor substrate is measured after the polishing process. Then, a polishing rate is calculated based on the reduced film thickness and the period of time of the polishing process. Subsequently, an optimal polishing time for subsequent substrates is calculated based on the calculated polishing rate and a desired film thickness. Thus, subsequent substrates are polished for the calculated optimal polishing time.
Since the polishing rate has variations, the calculated polishing rate may be adaptable to only the polished substrate. In such a case, if the polishing rate thus calculated is simply used for the purpose of calculation of an optimal polishing time for subsequent substrates, then the film thickness of the subsequent substrates may considerably deviate from a desired value after polishing processes. Accordingly, it has been proposed to store data on the amount of polishing and polishing times for polished substrates in a storage device, calculate an average polishing rate based on the data in the storage device, and perform a subsequent polishing process for a period calculated based on the average polishing rate. With this method of calculating an average polishing rate based on the past data, it is possible to save troublesome measurements of polishing rates for each lot of substrates and reduce variations of measurements.
However, in the polishing apparatus, a polishing rate largely depends upon surface conditions of a polishing pad, conditions of a pad conditioner for conditioning a surface of the polishing pad, a composition and temperature of a polishing liquid, a temperature and pressure of a deposition process, a non-uniformity of properties of films due to variations of materials, and variations in polishing temperature. Thus, a polishing rate is not necessarily maintained stable at an average polishing rate.
As described above, in recent years, chemical mechanical polishing (CMP) has been employed to planarize irregularities of a surface which are produced during formation of an insulating film or an interconnect metal film in a process for manufacturing semiconductor devices on a semiconductor substrate. In CMP, a substrate to be polished is pressed against a polishing pad formed of a non-woven fabric. The substrate and the polishing pad are moved relative to each other so as to bring the substrate and the polishing pad into sliding contact with each other while abrasive particles are supplied between the substrate and the polishing pad. Thus, the substrate is polished. Concentric grooves or checked grooves formed in a surface of the polishing pad can effectively supply a sufficient amount of abrasive particles to a central portion of the substrate.
A polishing pad having a two-layer structure in which a relatively hard polyurethane foam layer is attached to a relatively soft non-woven fabric is effective in reducing an influence due to nanotopology, i.e., swell of a surface of a substrate. A polishing pad having a two-layer layer structure, such as IC-1000/SUBA400 manufactured by Rodel Inc., is well known. In order to remove polishing wastes attached to a surface of the polishing pad during CMP, pad conditioning is conducted to remove a portion of the surface of the polishing pad with a diamond disk. As a result of the pad conditioning, a depth of the grooves formed in the surface of the polishing pad and a ratio of a soft layer and a hard layer change with time according to abrasion of the polishing pad, thereby exerting a great influence on the polishing process.
With a conventional polishing method, in order to monitor changes of a polishing rate and a within wafer uniformity of polishing according to a change of the polishing pad with time, a quality control (QC) substrate (substrate having a film all over a surface thereof) is polished each time a predetermined number of product substrates, on which semiconductor devices are formed, are polished. A polishing rate is defined as a thickness of a film removed per unit time when a film formed on a substrate is polished under a predetermined pressure (e.g. 1.5 psi). Processing time for product substrates to be subsequently polished is adjusted based on the polishing results of the QC substrate mostly by an operator. Specifically, the operator manually calculates an optimal polishing time based on the polishing results of the QC substrate. Further, it has heretofore been attempted to provide a film thickness measurement device in a polishing apparatus to optimize a processing time based on the measurement results. With this method, a certain period of time is required to perform a feedback control, so that several substrates may be polished without optimization of the processing time.